In the formation of fine-lne metal oxide semiconductor (MOS) devices, a recurring and severe problem is hot carrier instability (HCI). This problem occurs due to high electrical fields between the source and the drain, particularly near the drain that cause carriers, either electrons or holes, to be injected into the gate or substrate. The injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance.
This problem has been addressed by attempting to reduce the strength of the electric field near the source and the drain regions. One approach concerns using a graded drain structure. For instance, in an n-channel device, a heavily doped drain of phosphorous or arsenic surrounded by a lighter doping of phosphorous is used to gradually extend the drain region into the channel region to reduce the electric field strength right at the drain. However, this approach is undesirable in that it causes larger overlap capacitance with the gate and channel shortening. Merely the deeper junction of the drain produces more disadvantageous short channel effects, such as an abrupt dropoff of threshold voltage with L.sub.eff.
With deeper junctions, there is a wider subsurface depletion effect and it is easier for the field lines to go from the drain to the source, which causes "punchthrough current" problems and shorts out the device.
A more satisfactory solution to the hot carrier instability problems concerns the use of lightly doped drains (LDDs). LDDs consist of a lightly doped source/drain region that is driven just under the gate region, while the heavily doped drain region is laterally displaced away from the gate by use of a sidewall spacer on the gate. LDDs are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely. For a discussion of various approaches to minimizing HCI effects, see E. Takeda, et al. "Submicrometer MOSFET Structure for Minimizing Hot-Carrier Generation," IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, April 1982, pp. 611-618.
Lightly doped drains have been studied most extensively in connection with n-channel MOS devices (NMOS) where the HCI problems are most severe. Some limited work has been done on using LDDs with p-channel devices (PMOS) where they provide drain to source punchthrough or short channel protection. For both types of devices the LDD structure has small lateral diffusion under the gate.
The lightly doped regions are implanted after the gate has been etched and prior to sidewall formation. The sidewall spacer is formed by first depositing a dielectric after the gate has been etched and then removing the dielectric from the horizontal regions, namely, the top of the gate, and the source and drain regions, using anisotropic etching, such as reactive ion etching (RIE). This process results in a sidewall spacer left behind on the gate sidewalls that has a roughly quarter-circular cross-section. For a description of this procedure, see Y. Matsumoto, et al. "Optimized and Reliable LDD Structure for lum NMOSFET Based on Substrate Current Analysis," International Electron Devices Meeting Papers, Vol. 15.4, 1983, pp. 392-395. See also U.S. Pat. No. 4,356,623, incorporated by reference herein. The spacer is typically a dielectric that remains on the gate sidewall through the final process. After sidewall spacer formation, a heavy source/drain implant is typically done with the gate and spacer acting as masking materials. Consequently, the heavily doped source and drain regions are laterally displaced from the gate edges by the thickness of the sidewall spacer material.
However, to form LDDs on complementary MOS integrated circuits (CMOS) which contain both NMOS and PMOS devices, the obvious technique for putting LDDs on the p-channel and n-channel devices would require the use of four lithographic steps using two different protective resist masks, which is an undesirably large number. The four steps would be an n.sup.- mask after gate etch, a p.sup.- mask, n.sup.+ mask (which may be the same as the n.sup.- mask) after the sidewall formation and a p.sup.+ mask (which may be the same as the p.sup.- mask). In addition to a large number of masking steps required in this straightforward approach, this technique requires that the p.sup.- region under the spacer of the PMOS gate will receive the same thermal cycle that the n.sup.- region receives at the end of the four implants. This will be deleterious to PMOS transistor behavior in that a large lateral diffusion of p.sup.- region under the gate of the PMOS device will produce short channel effects. In other words, greater underdiffusion, greater overlap capacitance and deeper p.sup.- junctions will occur along with the accompanying short channel effects, etc. Therefore, it would be desirable to provide a technique to incorporate LDDs in both n-channel and p-channel devices on a CMOS structure that requires only one or two mask levels and in addition, that separates the thermal cycles of n-type and p-type source/drain regions.
S. Ratham, et al. in "An Optimized 0.5 Micron LDD Transistor," International Electron Devices Meeting Papers, Vol. 10.2, 1983, pp. 237-241, describe a procedure for making LDDs where a lithographed photoresist layer protects the gate during implantation of the heavily doped source/drain regions and is then removed for the implantation of the LDD areas. Even though the protective photoresist mask is removable, the LDD formation step is not a self-aligned one and the number of mask levels required to implement LDDs in CMOS circuits would be undesirably high.